backup: Digital Circuit Course Design, Music Player with VGA Display

Busy with digital circuit labs. It’s been a long time since I coded QAQ. Nothing coded recently, so I just pull up the digital electricity course design QWQ~

Let’s start with a whole

This is the top of the whole project, and then it is separate to each module

Phase-Locked Loop Crossover

This Phase-Locked Loop is used for dividing the frequency. My FPGA board is a Cyclone IV and comes with a 20MHz clock signal. The buzzer needs 1MHz, the music needs 4KHz, and the VGA display 640 * 480 * 60Hz needs 25MHz

Music Module

This is the music module, mainly divided into the number of notes recorded constep, recorded notes Rom, notes converted into buzzer frequency INX2CODE and sound SPK0

The constep is simply a counter that records the number of notes stored in the mif.

The ROM is needed to turn the score into a mif file and then use the ROM module to generate the device.

INX2CODE

module INX2CODE (INX, F_CODE);
	input[3:0] INX;
	output[10:0] F_CODE;
	reg[10:0] F_CODE;
	always @(INX)
	case (INX)
	  0 : F_CODE <= 11'H7FF;
	  1 : F_CODE <= 11'H305;
	  2 : F_CODE <= 11'H390;
	  3 : F_CODE <= 11'H40C;
	  4 : F_CODE <= 11'H45C;
	  5 : F_CODE <= 11'H4AD;
	  6 : F_CODE <= 11'H50A;
	  7 : F_CODE <= 11'H55C;
	  8 : F_CODE <= 11'H582;
	  9 : F_CODE <= 11'H5C8;
	 10 : F_CODE <= 11'H606;
	 11 : F_CODE <= 11'H640;
	 12 : F_CODE <= 11'H656;
	 13 : F_CODE <= 11'H684;
	 14 : F_CODE <= 11'H69A;
	 15 : F_CODE <= 11'H6C0;
	default : F_CODE <= 11'H6C0;
		endcase
endmodule

SPK0

VGA Driver

Convert the image to bmp format, then to mif, and save it to ROM like a note to generate a device.

vga_driver

module vga_driver(
	clk,
	hs,vs,
	r,g,b,
	rgbin,dout
	);
	input clk;
	output hs,vs;
	output r,g,b;
	input rgbin;
	output[15:0] dout;
	reg[9:0] hcnt,vcnt;
	reg r,g,b;
	reg hs,vs;
	assign dout={vcnt[7:0],hcnt[7:0]};
	
	always @(posedge clk)
		if(hcnt<800)
			hcnt<=hcnt+1;
		else
			hcnt<={10{1'b0}};
	
	always @(posedge clk)
		if(hcnt==640+8)
			if(vcnt<525)
				vcnt<=vcnt+1;
			else
				vcnt<={10{1'b0}};
	
	always @(posedge clk)
		if((hcnt>=640+8+8)&(hcnt<640+8+8+96))
			hs<=1'b0;
		else
			hs<=1'b1;
			
	always @(vcnt)
		if((vcnt>=480+8+2)&(vcnt<480+8+2+2))
			vs<=1'b0;
		else
			vs<=1'b1;
	
	always @(posedge clk)
		if(hcnt<256&vcnt<256)
			begin
				r=rgbin;
				g=rgbin;
				b=rgbin;
			end
		else
			begin
				r=0;
				g=0;
				b=0;
			end
endmodule

Selector

module choose2_1(
	EN,
	badapple,sakura,
	HS1,VS1,HS2,VS2,
	SPK1,SPK2,
	R1,R2,G1,G2,B1,B2,
	SPK,R,G,B,HS,VS
	);
	input EN,badapple,sakura;
	input HS1,VS1,HS2,VS2;
	input SPK1,SPK2;
	input R1,R2,B1,B2;
	input G1,G2;
	output SPK;
	output HS,VS;
	output R,B;
	output G;
	reg SPK;
	reg HS,VS;
	reg R,B;
	reg G;
	always @ (
		EN,
		badapple,sakura,
		HS1,VS1,HS2,VS2,
		SPK1,SPK2,
		R1,R2,G1,G2,B1,B2
		)
		if(EN==1)
			begin
				SPK=1;
				R=0;
				G=0;
				B=0;
				VS=0;
				HS=0;
			end
		else
			if({sakura,badapple}==2'B10)
				begin
					SPK=SPK1;
					R=R1;
					G=G1;
					B=B1;
					VS=VS1;
					HS=HS1;
				end
			else
				if({sakura,badapple}==2'B01)
					begin
						SPK=SPK2;
						R=R2;
						G=G2;
						B=B2;
						VS=VS2;
						HS=HS2;
					end
				else
					begin
						SPK=1;
						R=0;
						G=0;
						B=0;
						VS=0;
						HS=0;
					end
endmodule

I do not have a VGA monitor can only go to a friend’s bedroom to play ~

Source code: Github